Pipeline synchronisation device

ABSTRACT

Pipeline synchronization device for transferring data between clocked devices having different clock frequencies. The Pipeline synchronization device comprises a mousetrap buffer for exchanging data with one of said external devices said mousetrap buffer having a signalling output for coordinating the data exchange with the external device. The pipeline synchronization device comprises further a synchronizer adapted to synchronizing the change in a signalling output with the clock of the external device.

The present invention relates to a pipeline synchronisation device fortransferring data between clocked devices having different clockfrequencies.

Future developments undermine the role of globally clocked VLSIcircuits. VLSI stands for very large scale integration. VSLI circuitshave between 100,000 and 1 million transistors on a chip. Globalclocking means, that all the components of the circuits are driven withthe same clock frequency. The trend towards the system on chip designsleads to chips containing several modules, which are driven withdifferent clock frequencies. In future technologies it will comeincreasingly difficult to distribute high speed low skew clock signals.Skew stands for a change of timing or phase in the clock signal, whichis a result of the time it takes for the signal to travel to themodules. Therefore, future chips will contain several locally clockedsubmodules, which communicate which each other. These systems are calledGALS (globally asynchronous, locally synchronous) systems. Two kinds ofsystems can be distinguished depending on the way the synchronoussubmodules communicate.

In a clock synchronization system, the submodules have so calledplausible clocks, which are ring oscillators that can be halted. Safecommunication is obtained by synchronizing the clocks.

In a data synchronization system, the submodules have free runningclocks and the data being communicated from one clock to the other issynchronized. Such a data synchronization system is known from J. N.Seizovic pipeline synchronization, in Proceedings InternationalSymposium on advanced research in asynchronous circuits and systems,pages 87 to 96, November 1994. A pipeline synchronization buffer,consists of three sections: a write section, an intermediate section anda read section. The write section synchronizes the input operations withthe write clock, while the read section synchronizes the outputoperations with the read clock. The intermediate section is anasynchronous buffer, which serves to decouple the two synchronizingsections. The design of all three sections is based on ripple buffers(asynchronous buffer). The transformation from a ripple buffer into asynchronizing buffer is presented in “pipeline synchronization” by J. N.Seizovic. This transformation is based on inserting in-between twoneighbouring cells a component that synchronizes the handshakes with theclock phase. The basic wait component (called wait 4), delays thecompletion of a four-phase-handshake until an additional signal clock ishigh. Since signal clocks can go low when the handshake starts, aconflict can occur implying that a so called arbiter is needed in thedesign of the component. A basic arbiter (also called mutual exclusionelement) has two incoming request signals and two outgoing acknowledgesignals. An acknowledge signal goes high when the corresponding requestsignal goes high and it goes low when the request signal goes low. Butthere is one restriction: At most one of the acknowledge signals may behigh. If one of the acknowledge signals is high and the other requestsignal goes high, the arbiter ignores the other request signal, untilthe acknowledge signal goes low. When both request signals go highsimultaneously, the arbiter has to decide which acknowledge signalshould go high first. When making the decision, the arbiter may remainin a metastable state for an unbounded period of time.

FIG. 6 shows the design of the wait 4-component based on a basicarbiter. The wait 4-component consists of a basic arbiter 60 and aninverter 65. An inverted clock signal is input in the basic arbiter 60.The acknowledge signal of the basic arbiter corresponding to theinverted clock signal is not used in the wait 4-component. Whenever theinverted clock signal is high and the corresponding output signal ishigh, the acknowledge signal e corresponding to the request signal d inFIG. 6 is low, irrespective of the request signal d. The acknowledgesignal e may only go from low to high if the inverted clock signal islow, i.e. the clock is high. An up-edge in signal d is only transferredduring the high phase of the clock. A falling edge in signal d istransferred immediately to signal e.

FIG. 1 shows the design of a conventional mousetrap buffer, which is aripple buffer using two phase single rail handshake signalling for thecommunication between neighbouring cells. Each cell has two signallingoutputs, a read request signal (Rreq) and a write acknowledge signal(WACK). The mousetrap buffer has two signaling inputs: a write requestinput (Wreq) and a read acknowledge input (Rack). The read requestoutput and the read acknowledge input are connected to an EXNOR-gate.The output of the EXNOR-gate controls a register of the mousetrapbuffer. If the signal en is high, all latches in the buffer aretransparent, which means that the outputs of the latches are equal tothe inputs. In this state data may be written to the mousetrap buffer.If the signal en goes low, the latches of a mousetrap buffer are madeopaque. As long as the buffer is opaque, no data may be transferred tothe buffer. A communication in a two-phase phase handshake protocolconsists of only two handshake events: first the sender indicates bymeans of a transition in a so-called request signal that new data isbeing offered. Then the receiver indicates by means of a transition inan acknowledge signal that the data has been received. It is importantto acknowledge, that the change in the request signal and the change inthe acknowledge signal indicate the respective events. The transition inthe request signal and the acknowledge signal may be either an up-edgeor a down-edge transition of the signal. Each two-phase communicationinverts the handshake signal therefore. This is in contrast to afour-phase handshake communication, which leaves the signals invariant.The four-phase handshake always starts with both signals low. Thetwo-phase handshakes start with both signals equal (either high or low).In the mousetrap buffer, the request signals are used to pass on dataitems (full buckets) and the acknowledge signals are used to make a fullbuffer empty (give back empty buckets). Passing a data item (fullbucket) is done via the request signals, whereas the acknowledge signalsare used to return an empty bucket. When data has been written to themousetrap buffer, the write acknowledge signal is made equal to thewrite request signal. Thereby an empty bucket is returned to thepreceding mousetrap buffer and a full bucket is transferred tosucceeding mousetrap buffer.

The mousetrap buffer has several properties that make it very attractivefor pipeline synchronization in GALS systems.

In many GALS (globally asynchronous, locally synchronous) systems theclock also implies distances, in which case the transmission delays areimportant. For this reason the two-phase protocol is more attractivethan a four-phase protocol. The mousetrap buffer is fast, which meansthat it allows high clock rates in the synchronizing buffers. Moreover,for a given clock frequency, a faster buffer has more time to deal withmetastable states which results in a smaller possibility ofsynchronization failure. An empty mousetrap buffer has a latency of onlyone latch delay per cell.

FIG. 2 shows how two mousetrap cells MS 1 and MS 2 are connected to eachother, in order to form an asynchronous (self-timed) pipeline. The readacknowledge input of mousetrap 1 is connected to the write acknowledgeoutput of mousetrap 2. The read request output of mousetrap 1 is equalto the write request input of a mousetrap 2. The read data out ofmousetrap 1 is equal to the write data input of mousetrap 2. Such abuffer cannot be used to bridge clock domains because the handshakesignals may change asynchronously (may not meet set up and holdrequirements).

It is therefore an object of the present invention to provide a pipelinesynchronization device, which operates fast and reliably.

The object is achieved by a pipeline synchronization device fortransferring data between clocked external devices having differentclock frequencies. The pipeline synchronization device comprises amousetrap buffer for exchanging data with one of the external clockdevices. The mousetrap device may either read or mix data from anexternal device or write data to an external device. The mousetrapbuffer has a signalling output for reconciling the data exchange withthe external device. The signalling output may be either a writeacknowledge signal to an external device, that writes data into themousetrap buffer, or a read request signal for transferring data to anexternal device. The synchronizer is adapted to synchronizing the changein a signalling output with the clock of the external device. The changein the signalling output may be either an up edge or a down edge signal.The mousetrap buffer is a ripple buffer. The signalling outputs maychange asynchronously. Therefore, the mousetrap buffer may notcommunicate with an internally clocked device. Due to the synchronizer,the signalling output of the mousetrap buffer may meet set-up and holdrequirements of the external device made. In this way the mousetrapbuffer may be used in pipeline synchronization.

The synchronizer may be adapted to synchronizing the changing signallingoutput with a high phase or a low phase of the clock of the externaldevice. In other words, an up edge or a down edge in the signallingoutput is only transferred, if the clock of the external device iseither high or low. To this end, the synchronizer delays a transfer ofthe change in the signalling output until the clock of the externaldevice is either high or low. If the clock is either high or low tobegin with, i.e. when the change in the signalling output occurs, thesynchronizer does not delay the transfer. In this way the set-up andhold requirements of the external device may be met.

Preferably the synchronizer comprises a synchronizing latch. Thesynchronizing latch has a synchronizing input for receiving thesignalling output. The latch further comprises a synchronizing outputfor outputting the received signalling output to the external device anda control input for enabling the output of this received signallingoutput to the external device. When the control input is high, the latchbecomes transparent and the signal input to the latch becomes equal tothe signalling output from the latch. The synchronizing latch is usedfor delaying the transfer of a change in the signalling output, untilthe control input enables the latch.

The synchronization of the control input with a clock phase of theexternal device may be accomplished in the following way: thesynchronizer further comprises an EXNOR-gate. The EXNOR-gate has twoinputs and one output. The inputs of the EXNOR-gate are connected to thesynchronizing input and output of the synchronizing latch. If no changein the signalling output of the mousetrap buffer occurs, the inputs andoutputs of the EXNOR-gate are equal. Consequently, the EXNOR-gate isclosed, i.e. the output of the EXNOR-gate is low. If the signallingoutput of the mousetrap buffer changes, the input and output of thesynchronizing latch will differ. Consequently, the EXNOR-gate is opened,i.e. the output of the EXNOR-gate is high. The synchronizer furthercomprises a wait-component, which is connected to the output of theEXNOR-gate and the clock of the external device. The output of thewait-component is connected to the control input of the synchronizinglatch. The wait-component synchronizes the control input of thesynchronizing latch with a phase of the clock of the external device.Preferably the wait-component is adapted to outputting the change fromlow to high in the input only, if the clock of the external device ishigh. The output of the wait-component remains low if the clock of theexternal device is low, even if the input of the wait-component is high.The output of the wait-component remains high, if the input is high, isrespective of the state of the clock. A change from high to low in theinput is output immediately is respective of the state of the clock ofthe external device. Therefore, a high output of the EXNOR-gate is onlytransferred to the control input, if the clock is high. Thereafter thecontrol input remains high as long as the EXNOR-gate is high. TheEXNOR-gate is low, if the synchronizing input and synchronizing outputof the synchronizing latch are equal. A high control input equalizes thesynchronizing input and the synchronizing output.

Preferably the wait-component comprises an inverter and an arbiter. Anarbiter has two inputs and two outputs. In general, an output signal ofthe arbiter goes high, if the corresponding input signal goes high andthe output signal goes low, if the corresponding input signal goes low.But there is a exception to this rule due to the restriction, that atmost one of output signals may be high. If one of the input signals ishigh and the other input signal goes high, the arbiter ignores the otherinput signal. This means that the output signals remain unchanged. Theoutput signal corresponding to the other input signal remains low. Oneof the inputs of the arbiter receives the inverted clock signal of theexternal device. The inverter inverts the clock signal. The other inputof the arbiter is adapted to receiving the output of the EXNOR-gate. Theoutput of the arbiter corresponding to the EXNOR-gate input is used fortransmitting the input. The other output of the arbiter has no functionin the wait-component. If the clock signal of the external device islow, the corresponding input of the arbiter is high.

The previously discussed implementations of the present invention relateto phase synchronization. This means that the change in the signallingoutput is synchronized with a high phase or a low phase of the clock ofthe external device. Preferably the synchronizer may be adapted tosynchronizing the change in the signalling output with a rising and/or afalling edge of the clock of the external device. An edge synchronizermay be put into practice by the use of two-phase synchronizers, whichare each adapted to delaying a transfer of a change in the signallingoutput until the clock of the external device is either high or low. Twomousetrap buffers are provided. A first mousetrap buffer is connected tothe external device and a second mousetrap buffer is connected to thefirst mousetrap buffer. A first synchronizer of the two synchronizerssynchronizes the signalling output of the first mousetrap buffer to theexternal device with an up phase or a low phase of the external clock.The second synchronizer synchronizes the signalling output of the secondmousetrap to the first mousetrap buffer with the other phase of theexternal clock. The signalling input to the first mousetrap buffer issynchronized for example with a low phase of the external clock. Thesignalling output of the first mousetrap buffer is generated inresponse. In general, the signalling output will be transmitted to thefirst synchronizer during the low phase of the external clock. The firstsynchronizer delays the transfer of the signalling output to the firstmousetrap buffer, until the external clock is high. In this example, thesignalling output of the first mousetrap buffer is synchronized with theup edge of the external clock.

The latch synchronizer may also be implemented by using twowait-components. Each of the two wait-components synchronizes a changein the input with a phase of an external clock. Both wait-componentshave two inputs. One input for receiving an external clock and anotherinput for receiving a signal to be transmitted. The change in the inputsignal is only transmitted, if the received clock signal is high. Oncethe output of such a wait-component is high, it remains high until theinput signal changes from high to low, irrespective of the state of thereceived clock. The two wait-components are connected with each other.The first wait-component outputs a signal to the external device and thesecond wait-component receives the signalling output from the mousetrapbuffer. The second wait-component receives an inverted clock from theexternal device, whereas the first wait-component receives the clock ofthe external device. The second wait-component transmits a change fromlow to high in the signalling output to the first wait-component, onlyduring a low phase of the external clock. The first wait-componenttransmits a change in the output of the second wait-component onlyduring a high phase of the external clock. Therefore, the signallingoutput is synchronized with the up edge of the external clock. Thesynchronization only takes place for the up edge of the signallingoutput, since the wait-components do not synchronize a change from highto low in the inputs with an external clock phase.

In order to synchronize both an up edge and a down edge of thesignalling output with an external clock edge, further components areneeded. To this end the synchronizer comprises a synchronizing latchhaving a synchronizing input and a synchronizing output. Thesynchronizing input receives the signalling output of the mousetrapbuffer. The synchronizing output is connected to the external device.The synchronizing latch further has a control input. A change betweenthe synchronizing input and synchronizing output of the synchronizinglatch is only transferred to the external device, if the control inputof the synchronizing latch is high. If the control input is high, thesynchronizing output of the latch is made equal to the synchronizinginput. The synchronizing input and the synchronizing output of thesynchronizing latch are both connected to the inputs of an exclusivenor-gate. The output of the EXNOR-gate is low, as long as thesynchronizing inputs and outputs are equal. The output of the EXNOR-gateis high, if the synchronizing input and synchronizing output differ. Ahigh EXNOR-gate output indicates a change in the signalling inputprovided to the synchronizing latch. The output of the EXNOR-gate isused for controlling the latch. If the output of the EXNOR-gate issynchronized with a clock edge of the external device, then it enables atransfer and a change of the signalling output is synchronous with theedge of the clock.

The embodiments of the present invention are described below withreference to the accompanied drawings.

FIG. 1 shows a mousetrap buffer according to the state of the art.

FIG. 2 shows two mousetrap buffers according to the state of the artconnected to each other,

FIG. 3 shows a write section of a pipeline synchronization deviceaccording to a fist embodiment of the present invention,

FIG. 4 shows a read section of the pipeline synchronization deviceaccording to the first embodiment of the present invention,

FIG. 5 shows the synchronizer of the first embodiment of the presentinvention,

FIG. 6 shows the wait-component of the synchronizer of the firstembodiment,

FIG. 7 shows a synchroniser of a second embodiment of the presentinvention,

FIG. 8 shows a four-phase up-edge component (UE4) used in thesynchroniser of FIG. 7,

FIG. 9 shows a mousetrap buffer of a pipeline synchronisation deviceaccording to a second embodiment of the present invention,

FIG. 10 a shows a write section of a pipeline synchronisation deviceaccording to a third embodiment of the present invention, and

FIG. 10 b shows a read section of a pipeline synchronisation deviceaccording to the third embodiment of the present invention.

FIG. 11 shows a pipeline synchronisation device according to a fourthembodiment of the present invention.

The write section of the pipeline synchronization device according tothe first embodiment shown in FIG. 3 comprises a mousetrap buffer (MT)and a synchronizer (S). The mousetrap buffer MT and the synchronizer Sare connected to a write device WD. The write device has an internalclock CLK which is output to the synchronizer S. The synchronizer Ssynchronizes the write acknowledge signal Wack of the mousetrap bufferMT with the clock CLK of the write device WD. The mousetrap buffer MT inFIG. 3 corresponds to the conventional mousetrap buffer shown in FIG. 1.The write acknowledge signal Wack changes from high to low or from lowto high, if the data Wdat have been written to the mousetrap buffer MT.Simultaneously the mousetrap buffer MT is made opaque, which means thatfurther data may not be written into the mousetrap buffer MT. Themousetrap buffer MT changes the read request signal Rreq. This signalchange indicates that the data may be read from the mousetrap buffer MT.The synchronizer S delays the transfer of a change in the writeacknowledge signal to the write device WD. The change in the writeacknowledge signal Wack may consist of both an up edge and a down edgetransition. Since the mousetrap buffer MT operates according to atwo-phase protocol, both an up edge and a down edge transition of thewrite acknowledge protocol may indicate, that the buffer has receivedthe write data Wdat. Thereby, the write device is notified, thatadditional data may not be written to the mousetrap buffer MT until thewrite acknowledge signal changes once again. The write acknowledgesignal must be received in synchronicity with the internal clock of thewrite device, so that the write device may process the signalling outputof the mousetrap buffer MT.

FIG. 4 shows the read section of the pipeline synchronization deviceaccording to the first embodiment. The mousetrap buffer MT in FIG. 4 isconnected to a read device RD, which reads data Rdat from the mousetrapbuffer. The signalling of the mousetrap buffer MT to the read device RDmust be synchronized with the clock CLK of the read device RD. To thisend a synchronizer S corresponding to the synchronizer S in FIG. 3 isinserted between a read request output of the mousetrap buffer MT and aread request input of the reading device RD. The internal clock of thereading device RD is input to the synchronizer S. The synchronizer Sdelays the transfer of a change in the read request signal Rreq to thereading device RD. Therefore, the read request signal change issynchronized with the internal clock CLK of the read device.

FIG. 5 shows the synchronizer used in FIG. 3 and 4 according to thefirst embodiment. The synchronizer S in FIG. 5 comprises a latch Lhaving an input SI and an output SO. The synchronizing input SI in FIG.5 corresponds to the write acknowledge signal Wack in FIG. 3 and to theread request signal Rreq in FIG. 4. The synchronizing output SO in FIG.5 corresponds to the output of the synchronizer as to the write deviceWD in FIG. 3 and to the read device RD in FIG. 4. The synchronizingoutput SO of the latch L is made equal to the synchronizing input SI ofthe latch, if a control input E to the latch L is high. A change in thesignalling output of the mousetrap buffer MT in FIG. 3 and 4 correspondsto a change in the synchronizing input SI and the synchronizing outputSO of the latch L. The transfer of this signalling output transition issynchronized with the clock CLK of the write device WD or the readdevice RD by means of wait-component wait 4. The wait 4-componentsynchronizes the control input of the latch L with the external clockCLK. Because of an EXNOR-gate 50 connected to the input SI and theoutput SO, the input d of the wait-for-component is high, if the inputSI and the output SO differ, and low, if SW input SI and the output SOare equal. A change from low to high in the signal d is indicative of achange in the signalling output of the mousetrap buffer MT. The wait4-component delays an up edge in signal d, until the clock CLK is high.Therefore, the control input D of the latch L may only change from lowto high during a high phase of the clock CLK. Consequently, an up edgeor a down edge in the signalling output in FIG. 3 and 4 is synchronizedwith the high phase of the corresponding clocks CLK of the write deviceWE) or the read device RD.

FIG. 6 shows a design of the wait 4-component in FIG. 5. The wait4-component comprises an arbiter 60 and an inverter 65. The inverter 65inverts the clock signal CLK of the external device WD or RD. Thearbiter 60 has two outputs. Only one of the two outputs, namely outpute, is used in the wait-for-component. Output e of the arbiter 60 is theoutput that corresponds to the input d of the arbiter 60. This means,that signal e is equal to signal d in all times, unless the secondoutput of the arbiter 60 corresponding to the inverted clock signalinput is high.

FIG. 7 shows a two-phase edge synchroniser, which is used in a secondembodiment of the present invention. The synchroniser of FIG. 7 has thesame design as the synchroniser shown in FIG. 5 with one exception: Thewait4-component in FIG. 5 is replaced by a four-phase up-edge componentUE4. The four-phase up-phase up-edge component UE4 is designed tosynchronise the transition of an up-edge transition in the input signald with an up-edge of the external clock CLK. The components surroundingthe UE4 component are responsible for transforming the four-phaseup-edge component UE4 into a synchroniser, which synchronises both theup-edge and the down edge of a signal with an up-edge transition in theclock CLK. The EXNOR-gate 50 has a low output d as long as the inputsignal SI and output signal SO are equal to each other. If SI and Sodiffer in any way, the EXNOR-gate 50 has a high output d. A down-edgetransition in signal SI and an up-edge transition in signal SI both leadto a high output of the EXNOR-gate 50. The EXNOR-gate does not discernbetween up-edge and down-edge transitions. Therefore, both up-edge anddown-edge transitions are synchronised by the component UE4, whichreceives an up-edge signal d from the EXNOR-gate 50, whenever an up-edgeor down-edge transition occurs in the signal SI. The up-edge signal d issynchronised with an up-edge of the clock CLK by the UE4-component. Thesynchronised signal is output to the control input e of the latch L,which in turn makes the output signal SO equal to the input signal SI.Thereby, a change in the input signal is transferred synchronous withthe up-edge of the clock CLK.

FIG. 8 shows the design of a four-phase up-edge component UE4, which maybe used in the synchroniser shown in FIG. 7. The component UE4 isconstructed by connecting two wait4-components to each other. A firstwait4 component receives the signal d, which is to be synchronised. Asecond wait4 component receives the output ar of the first wait4component. An inverter 80 inverts the external clock signal CLK. Theinverted clock is input to the first wait4 component. The second wait4component receives the clock signal CLK. An up-edge in the signal inputd is only transferred during the low phase of the clock CLK, i.e. whenthe clock input of the first wait4 component is high. In this case thesignal ar input to the second wait4 component is high, but the clockinput of the second wait component is low. The output signal e remainslow, until the clock CLK goes from low to high. The output ar of thefirst wait4 component is not affected by a change in the clock CLK aslong as the input d is high. Therefore an up edge in signal d issynchronised with an up edge in the clock CLK. At falling clock edgesthe delay of the inverter 80 takes care of closing the second wait4component before the first one is opened.

FIG. 9 shows the design of a mousetrap buffer according to a secondembodiment of the invention. The mousetrap buffer shown in FIG. 7 hasall the components, which the conventional mousetrap buffer shown inFIG. 1 possesses. Identical reference signs in FIG. 1 and 7 indicate thesame features. In addition, the mousetrap buffer in FIG. 7 comprises asynchroniser (s). The synchroniser (s) synchronises the signal d outputfrom the EXOR-gate of the mousetrap buffer with the clock of an externalwrite device (not shown). For this purpose the synchroniser (s) receivesthe clock (CLK) of the write device. The design of the mousetrap bufferis such, that the signalling output (Wack) to the write device issynchronised with the clock (CLK) of the write device. Thesynchronisation of the signalling output has been integrated into themousetrap buffer.

The design of the buffer makes use of the fact, that the control input(e) of the latch (L) executes a four-phase-handshake protocol thatstarts at the arrival of an empty bucket (latch is made transparent).Therefore, the arrival of empty buckets can be synchronised byincorporating a four-phase synchroniser (s) in the latch control of themousetrap cell. The design of a phase synchroniser is much simpler thanthe design of an edge synchroniser. Therefore, the synchronisationoverhead is reduced. However, since the cell only synchronises thearrival of empty buckets, it can only be used in the write section ofthe buffer. As a result the performance of the write section isimproved. The write section of the mousetrap buffer is in general slowerthan the read section. Passing a data item (full bucket) from themousetrap buffer is done via the request signals, whereas theacknowledge signals are used to return an empty bucket. The speed forpassing a data item is limited by the delay of the latch. The speed forpassing an empty bucket is limited by the delay of the EXNOR-gate andthe latch. Therefore, passing empty buckets is the bottleneck, when thebuffer runs at full speed. Due to the integration of the synchronisingcomponent in the mousetrap buffer, the write section offers about thesame performance as the read section.

The UE4 component as integrated in the latch-enable control circuit willsynchronize the arrival of Rack with the Clk. After this, the latchesare transparent and signal Wack follows signal Wreq directly. As signalWreq originates from the synchronous domain driven by the Clk, and thusis synchronous with this Clk, signal Wack is also synchronized with theClk. In a way, during this synchronization, Wack depends combinationallyon Wreq, and is merely a delayed version of this signal. In the clockeddomain, this assumes a clocked register in the path from Wack to Wreq soas to compute the new value of Wreq for the next clock cycle.

FIG. 10 a shows the design of a write section of a pipelinesynchronisation device according to the present invention. The writesection is the part of the pipeline that receives data from a writedevice (not shown). The write section largely corresponds to theasynchronous pipeline comprising two mousetraps shown in FIG. 2. Thefirst mousetrap MT1 in FIG. 10 a is connected to a write device WD (notshown). The connection to the write device is established in the sameway shown in FIG. 3. The write acknowledge signal of the first mousetrapMT1 is fed to the write device via a synchroniser. A first wait2synchroniser is used, which synchronises an up-edge and a down-edgetransition in the Wack signal of mousetrap MT1 with a high clock phase.A second wait2 component is provided between the first and secondmousetrap buffer MT1 and MT2. The write acknowledge signal from themousetrap 2 is synchronised with an inverted clock signal. This meansthat a change of the write-acknowledge signal from mousetrap MT2 is onlytransferred to mousetrap MT1, if the clock is low. The write acknowledgesignals are responsible for passing empty buckets from mousetrap tomousetrap. An up-edge or a low-edge in the write acknowledge signal fromthe second MT2 to the first mousetrap MT2 is transmitted during a lowphase of the external clock CLK. Consequently the first mousetrap bufferMT1 is made empty and the state of the write acknowledge signal of thefirst mousetrap to the write device is changed. If this change takesplace during the low phase of the external clock, the signal is nottransmitted due to the wait2 component transmitting the signal Wack tothe write device WD. The transfer is delayed until the clock is high,i.e. during the up-edge transition of the clock. The design presented inFIG. 10 a is an up-edge synchronisation circuit for the write section ofa pipeline synchronisation device according to the present invention.

FIG. 10 b depicts the corresponding design of a read section of apipeline synchronisation device according to the present embodiment.This embodiment synchronises the Rreq signal with Rclk, but it has onedisadvantage. Since the Rreq is only synchronised with the high periodof Rclk, the synchronous domain (assuming it is positive-edge triggered)is actually informed too late about new data arriving at Rdat.Therefore, the synchronous domain has to be allowed one clock cycle toabsorb that new data on the next Rclk edge. The dependency of Rack onRreq thus requires a clock delay (e.g. a flip-flop), which reduces thethroughput (as seen from the synchronous domain) by 50%. The preferredembodiment is therefore one where the Rreq signal is not synchronisedwith Rclk directly, but rather a precursor of it is. This is obtained byshifting the synchronising wait components a single mousetrap stage tothe left, as shown in FIG. 11.

FIG. 11 shows another embodiment of the present invention, wherein twowait components are inserted between neighbouring mousetrapsconsecutively. The wait components both receive an external clocksignal, wherein one of said wait components comprises an inverter, whichinverts the clock signal received. The difference between the circuitshown in FIG. 11 and the circuit shown in FIG. 10 b is the location ofthe wait components in the pipeline. In FIG. 10 b one of the waitcomponents is located at the interface between the pipeline and theexternal read device. This is not the case in the pipeline shown in FIG.11. The circuit shown in FIG. 11 is a preferred alternative for thecircuit in FIG. 10 b, and is to be used for read synchronisation.

1. A pipeline synchronization device for transferring data betweenclocked devices having different clock frequencies, comprising: amousetrap buffer for exchanging data with one of the clocked devices,the mousetrap buffer including a signalling output for coordinating thedata exchange with the clocked device, and a synchronizer that isconfigured to synchronize a change in the signalling output with a clockof the clocked device, wherein the synchronizer includes: asynchronizing latch includes: a synchronizing input for receiving thesignalling output; a synchronizing output for outputting the receivedsignalling output to the clocked device; and a control input forenabling the output of the received signalling output to the clockeddevice, and an EXNOR-gate having two inputs and one output, the inputsof the EXNOR-gate being connected to the synchronizing input and outputof the synchronizing latch, and the synchronizer includes await-component having an input connected to the output of theEXNOR-gate, an input connected to the clock of the clocked device and anoutput connected to the control input of the synchronizing latch.
 2. Thedevice of claim 1, wherein the synchronizer synchronizes the change inthe signalling output with a high phase or a low phase of the clock ofthe external device.
 3. The device of claim 2, wherein the synchronizerdelays a transfer of the change in the signalling output until the clockof the clocked device is in a given state.
 4. The device of claim 1,wherein the wait-component signals a change from low to high of theinput if the clock of the clocked device is in a given state, andsignals a change from high to low of the input irrespective of the stateof the clock of the clocked device.
 5. The device of claim 4, whereinthe wait-component comprises an inverter and an arbiter having an inputfor receiving an inverted clock signal from the inverter, and an inputfor receiving the output of the EXNOR-gate and an output fortransmitting the input.
 6. The device of claim 1, wherein thesynchronizer synchronizes the change in the signalling output with arising and/or a falling edge of the clock of the clocked device.
 7. Thedevice of claim 6, wherein the synchronizer includes two synchronizersfor delaying a transfer of a change in the signalling output until theclock of the clocked device is in a given state, wherein a first of thetwo synchronizers transfers a change in the signalling output of a firstmousetrap buffer to the clocked device and wherein a second of the twosynchronizers receives an inverted clock of the clocked device andtransfers a signalling output of a second mousetrap buffer to the firstmousetrap buffer.
 8. The device of claim 6, wherein the synchronizerincludes an edge synchronizer that includes two wait-components, eachsigna1ing a change from low to high in the input if a received clock isin a given state, and signaling a change from high to low in the inputirrespective of the state of the received clock, wherein a first of thetwo wait-components receives the clock of the clocked device and signalsa change in its input to the clocked device, and wherein a second of thetwo wait components receives an inverted clock from the clocked deviceand signals a change in its input to the first wait component.
 9. Thedevice of claim 8, wherein the synchronizer includes a synchronizinglatch having a synchronizing input for receiving the signalling output,a synchronizing output for outputting the received signalling output tothe clocked device and a control input for enabling the output of thereceived signalling output to the clocked device.
 10. The device ofclaim 9, wherein the synchronizer includes an EXNOR-gate having twoinputs and one output, the inputs of the EXNOR-gate being connected tothe synchronizing input and output of the synchronizing latch, and thesynchronizer includes an edge synchronizer having an input connected tothe output of the EXNOR-gate, an input connected to the clock of theclocked device and an output connected to the control input of thesynchronizing latch.
 11. The device of claim 1, wherein the mousetrapbuffer receives data from the clocked device and the mousetrap bufferincludes a signalling output for acknowledging the receipt of data tothe clocked device.
 12. The device of claim 11, wherein the mousetrapbuffer includes an EXOR-gate for receiving a read request signal and aread acknowledge signal, a latch having a control input for enabling anddisabling the receiving and transferring of data, wherein thesynchronizer synchronizes an output of the EXOR-gate with the clock ofthe clocked device and supplies the output of the EXOR-gate to thecontrol input of the latch.
 13. The device of claim 12, wherein thesynchronizer synchronizes a change in the output of the EXOR-gate with arising and/or a falling edge of the clock of the clocked device.
 14. Thedevice of claim 1, wherein the mousetrap buffer transfers data to theclocked device and the mousetrap buffer includes a signalling output forrequesting the transfer of data to the clocked device.
 15. A method fortransferring data between clocked devices having different clockfrequencies, comprising: exchanging data with one of the clocked devicesvia a mousetrap buffer that is configured to output a signal forcoordinating the data exchange with the clocked device, andsynchronizing changes in the output signal with the clock of the clockeddevice using a synchronizer, wherein the synchronizer includes: asynchronizing latch includes: a synchronizing input for receiving thesignalling output; a synchronizing output for outputting the receivedsignalling output to the clocked device; and a control input forenabling the output of the received signalling output to the clockeddevice, and an EXNOR-gate having two inputs and one output,the inputs ofthe EXNOR-gate being connected to the synchronizing input and output ofthe synchronizing latch, and the synchronizer includes a wait-componenthaving an input connected to the output of the EXNOR-gate, an inputconnected to the clock of the clocked device and an output connected tothe control input of the synchronizing latch.